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andremanuel_3

Little/Big endian slide mistake in PTP??

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andremanuel_3

Hello, I think the slide 92 of the Architecture Fundamentals section has a mistake, please correct me if I'm wrong.

In slide 90 if states that the system is little-endian, so LSB is stored in the lowest memory  address and the MSB in the highest memory address, and the table representation in slide 91 confirms that.

But in slide 92 the address representation is inverted. 

Is this correct?

2034790550_Screenshot2020-08-02at16_21_01.thumb.png.a3cdd5dd023513098b220ea4f89b329a.png

163610574_Screenshot2020-08-02at16_21_14.thumb.png.1e047720e8fb3b9d19d025f7d58537bb.png
338705914_Screenshot2020-08-02at16_20_35.thumb.png.a84b0e8b9733cd20f5d0639fcf8c5457.png

Cheers

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andremanuel_3

This in the PTP course, section 1 Architecture Fundamentals

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gregels

I think correct as shown-

The LSB (0x0B) is stored at the lower address 0x0028FEBC of the register shown. 0x0028FEBC is the first byte of the 8 byte register.

 

 

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